Prototype schematic

Video digitalization

The video decoder is a TVP5150AM1 from Texas Instruments. This is a low power video decoder that can process PAL, NTSC and SECAM video in composite or s-video format. Both an S-video and composite connector are available but there is no analog switch which means they cannot be connected at the same time. This is done to reduce the cost. The chip decodes the video signal and digitizes it. Its output is in the digital ITU-R BT.656 format. This is a commonly used digital video format which consists of 8 data lines and a 27MHz pixel clock. Horizontal and vertical sync are embedded in the datastream as special markers.

Power supply

The main power for the board is a 3.3V line. To reduce costs and because power usage is low, a linear regulator is used. This does mean that the supply voltage should not be a lot higher than 3.3V because of the heat that needs to be dissipated. A 4.5V power supply should suffice. The LP8345 is a commonly used regulator and is stable with a couple of small ceramic capacitors. A P channel MOSFET (IRF7416) is used to protect against wrong polarity.

The video decoder needs both a digital and analog 1.8V rail. Also, the board is designed to be compatible with both the T and GT versions of the EPM570 CPLD. The GT version needs an additional 1.8V core voltage while the T version has an internal regulator for its core voltage. To reduce noise the digital and analog voltage lines will have an LC low-pass filter.

CPLD

Because the digital video signal produced by the video decoder is too fast for a simple microcontroller like the AVR a CPLD is used to process the video signal into a format the microcontroller can handle. A CPLD from Altera's MAX II series will be used, the EPM570 with 570 logic elements. While a CPLD does not have as much logic elements as a FPGA it is sufficient to do the very simple operations with the video data required for the applications of Chameleon. To reduce costs and the need for a separate configuration memory, a CPLD was chosen over an FPGA. The CPLD will contain a video scaler that scales the large video images down to a small matrix of average colors (probably 8x8).

Another task for the CPLD will be the hardware PWM channels. Since AVR microcontrollers only have a few PWM channels and software PWM is difficult because of the computation time for the lighting algorithms itself the CPLD will take care of this.

The PWM controllers will drive on board power FETs so that it can directly drive the low side of LEDs and CCFLs. For most purposes this is the easiest way to connect the lights. The logic PWM outputs will also be available directly so that other light configurations can be connected with custom hardware.

IRLML2502 N-Channel MOSFETs are used for the PWM outputs. They are capable of handling several amps but are low cost and come in a small SOT-23 package.

USB connection

An FT232R from FTDI makes it possible to connect the board with a PC. The standard serial connection it provides is used to communicate with the AVR. PC software will be written to change settings and color profiles for the board.

The FT232R is also used to program the AVR, and indirectly the CPLD. Using its synchronous bitbang mode the AVR can be programmed and updated without the need of an AVR programmer. Unlike standard bitbanging over USB, synchronous bitbang is actually quite fast and should be able to program the AVR in a short time. The CPLD will be programmed via a boot loader in the AVR and the USB connection so that no special programmers are needed for the CPLD either.

The FT232R USB-serial converter chip will provide the USB connection. It has several other lines connected to the ISP programming pins of the AVR so that the microcontroller can be programmed over USB without the need of a programmer or any additional hardware.

Microcontroller

For the main lighting algorithm an Atmel AVR will be used. The ATmega324P device will provide sufficient flash memory and I/O pins. The board will be designed to be compatible with the ATmega32 as well. The AVR receives the reduced color matrix from the CPLD and applies an algorithm to it to produce the final colors. It controls the PWM controller in the CPLD to drive the LEDs or CCFLs.

The AVR in the prototype will be an ATmega32. In the final design this will likely be changed to the pin compatible, newer and cheaper ATmega324P. The clock will run at 8Mhz, the maximum for an ATmega32 at 3.3V (although the ATmega324P can handle 10Mhz at this voltage). CLRDATA is an 8-bit parallel interface that is used to read the color matrix from the CPLD. Furthermore it has some other connections to the CPLD as well as a serial interface (TXD, RXD, RTS and CTS (not shown)).

The EPM's power connections (VCCINT) are connected via 0 ohm option resistors to connect either to 3.3V (VCC) or the digital 1.8V line, depending on which version of the CPLD is used (GT or T).